A Hybrid SRAM/RRAM In-Memory Computing Architecture Based on A Reconfigurable SRAM Sense Amplifier

In this paper, a hybrid memory architecture based on new array of SRAM and resistive random-access (RRAM) cells is proposed to perform in-memory computing by implementing all basic two-input Boolean functions. The can be configured as dual-purpose element. It used an in mode keep data for high-performance application requirements. also sense amplifier (SA-SRAM) reading the contents RRAMs performing computation. circuits are designed using independent-gate FinFET (IG-FinFET), whose channel controlled two independent gates, increasing design’s maneuverability. Our results indicate that SA-SRAM cells’ write energy consumption combined word line margin (CWLM) achieve 50% 20% improvements compared conventional 8T SRAM. Moreover, benefiting from combination RRAM architecture, our design areas, such image processing, much lower than well-known designs. addition, address security concerns, we polymorphic circuit primitive prevent reverse engineering or integrated (IC) counterfeiting. adds more computations accomplish complex logic operations architecture.